PMU overview

This document describes the behavior, billing, and limitations of the performance monitoring unit (PMU) in Compute Engine. The PMU is available only on C4 virtual machine (VM) instances.

The PMU is a hardware component within the CPU core that monitors how the processor runs code. By enabling the PMU in a C4 VM, you can use performance-monitoring software on the VM to access the PMU's performance counters. These counters help you identify and address performance issues within the software running on your VM. This information is helpful to optimize performance-sensitive workloads, such as high performance computing (HPC) or machine learning (ML) workloads.

How the PMU works

The PMU is composed of a set of hardware counters called performance monitoring counters (PMCs). These counters are model-specific registers that count each time a low-level processor event, such as a branch misprediction or cache miss, occurs within the CPU. You can read and configure PMCs in the PMU by using performance-monitoring software such as Intel VTune Profiler.

By default, the PMU is disabled within VMs. To enable it, specify the types of low-level CPU events to track by enabling one of the following PMU types:

  • Architectural (ARCHITECTURAL): You can measure the following architectural performance events:

    • Branch instructions retired: The number of branch instructions retired. Use this event to measure your code's execution and identify potential performance bottlenecks.

    • Branch misses retired: The number of branch instructions that were mispredicted, causing the processor to stall and discard fetched instructions. If you see a high number for this event, then you can likely optimize the CPU performance.

    • Instructions retired: The number of instructions the CPU successfully processes. Use this event to measure the CPU's instruction throughput.

    • Top down slots: The number of available slots within a processor's pipeline that are used to simultaneously execute instructions. Use this event to understand how efficiently your code is using the processor's resources.

    • Unhalted core cycles: The number of core cycles when the thread is not halted—for example, due to power management or interrupts. Use this event to evaluate the overall usage of the processor.

    • Unhalted reference cycles: The number of reference cycles when the core is not halted—for example, when fetching data or instructions. The core is halted when it runs the HLT or MWAIT instructions. Reference cycles operate at a fixed frequency, providing a stable time reference even when the processor's speed changes to preserve energy. Use this event to measure the time spent on a task and identify performance bottlenecks in your code.

  • Standard (STANDARD): You can measure all events from the Architectural PMU type and any local events inside the CPU core, including level 2 (L2) cache events.

  • Enhanced (ENHANCED): You can measure all events from the Standard PMU type, any local events outside the CPU core, including level 3 (L3) cache events.

After you enable the PMU in a VM, the PMU runs in the background, continuously monitoring performance events using PMCs. You can optionally configure thresholds for specific PMCs using your preferred performance-monitoring software. If a PMC exceeds its designated threshold, then the PMU notifies the software.

Limitations

For the PMU, the following limitations apply:

  • You can only enable the PMU in C4 VMs that specify the Intel Xeon Scalable Processor (Emerald Rapids) 5th generation, which C4 VMs specify by default. For a full list of the supported performance events for this CPU platform, see emeraldrapids_core.json.

  • You can only enable the Enhanced PMU type in C4 machine types with 96 or 192 vCPUs.

Pricing

There are no costs associated with enabling or disabling the PMU in a VM.

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